1. Field of the Invention
The invention relates to a delay circuit, and in particular to a delay circuit to respectively adjust rising and falling edges of an input signal.
2. Description of the Related Art
FIG. 1 is a schematic diagram of a conventional delay circuit 100. Delay circuit 100 comprises delay inverters 101, 102 and 103 and delay inverse circuit 110. Delay inverse circuit 110 comprises PMOS transistor 111 (Positive-channel Metal Oxide Semiconductor Transistor), NMOS transistor 112 (Negative-channel Metal Oxide Semiconductor Transistor), and buffer 104. In addition, PMOS transistor 111 and NMOS transistor 112 form a CMOS (Complementary Metal Oxide Semiconductor) inverter.
Delay circuit 100 adjusts rising speed, falling speed and delay time of signals according to the charge capacity of PMOS transistor 111, the discharge capacity of NMOS transistor 112 and P/N ratio. However, conventional delay circuit 100 cannot separately adjust the delay time of rising and falling edges of a signal.